By Johan Huijsing, Michiel Steyaert, Arthur H.M. van Roermund
This 10th quantity of "Analog Circuit layout" concentrates on three subject matters: Scalable Analog Circuits, High-Speed D/A Converters, and RF strength Amplifiers. each one subject is roofed by means of 6 papers, written by way of foreign famous specialists on that subject. those papers have an academic nature aimed toward bettering the layout of analog circuits. The booklet is split into 3 components: half I, Scalable Analog Circuit layout describes in 6 papers problems with: scalable high-speed layout, scalable high-resolution mixed-mode ADC and OpAmp layout, scalable high-voltage layout for XDSL, scalability of wire-line entrance ends, reusable IP analog layout, and porting CAD analog layout. half II, High-Speed D/A Converters describes in 6 papers problems with: advent to high-speed D/A converter layout, retargetable 12-bit 200-MHz CMOS present steerage layout, high-speed CMOS D/A converters for upstream cable purposes, static and dynamic functionality barriers, the linearity problem of D/A converters for communications, and a 400-MHz, 10-bit charge-domain CMOS D/A converter for low-spurious frequency synthesis. half III, RF energy Amplifiers describes in 6 papers problems with: process points, evaluate and trade-offs, linear transmitter architectures, GaAs microwave SSPAs, Monolithic transformer-coupling in Si-bipolar, and RF strength amplifier layout in CMOS. "Analog Circuit layout" is a vital reference resource for analog layout engineers and researchers wishing to maintain abreast with the newest advancements within the box. the educational assurance additionally makes it appropriate to be used in an strengthen layout direction.
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Additional resources for Analog Circuit Design: Scalable Analog Circuit Design
Letters, Vol. 31, pp. 1712-1713, 1995 27) “A High Resolution Multi Bit Sigma Delta Modulator with Digital Correction and Relaxed Amplifier Requirements” Sarhang-Hejad and 42 Temes, IEEE Jnl. of Solid State Circuits, Vol. 28, pp. 648-660, June 1993 28) “Fourth Order Two Stage Delta Sigma Modulator using both 1 Bit and Multi Bit Quantizers” Tan and Eriksson, Elec. Letters, Vol. 29, pp. 937-938, May 1993 29) “Multi Bit Sigma Delta A/D Converter Incorporating a Novel Class of Dynamic Element Matching Technique” Leung and Sutarja, IEEE Trans.
Rail-to-rail output stage design is well known  and the textbook methods appear adequately scalable with stacking of threshold and saturation voltages which can be accommodated within the shrinking supplies. ] with rail-to-rail common mode (CM) range appear challenging for high performance (MHz bandwidth and low THD) applications because of input offset shifting over the CM range as the input stage transitions between N- and P-MOS conduction. Two scalable architectures are shown. Both can use rail-to-rail output stages to maximise p-p signal swing and thus SNR.
This is eased by pumping or boot-strapping the gate voltage on the NMOS switches but of course this ideally should be as much as possible without exceeding the processes absolute maximum voltage rating. Gate boot-strapping methods have been developed to do this accurately [6,7,17]. The above collection of design features make for cheap, easy to use and robust converters which are suitable for scaling to deep submicron CMOS processes. Successive approximation converters are the subject of very little published work but of great commercial importance which is likely to continue into the foreseeable future.
Analog Circuit Design: Scalable Analog Circuit Design by Johan Huijsing, Michiel Steyaert, Arthur H.M. van Roermund