By Truman T.E.

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Logical link protocols are by nature distributed-state concurrent systems and the design process must insure the logical consistency of the protocol, and are thus the primary target for formal verification in our context1. This is because formal verification focuses on proving properties about the system given a set of possible events, without regard to the probability of any event. So, for example, one would like to prove that the logical link could not deadlock under packet reordering or loss events.

Thus, the main function of the hardware is to support data flow between multimedia sources (or sinks) and the wireless link. The core of the InfoPad hardware is a low-power bus, called the IPbus, dedicated to the movement of I/O data. Attached to this bus in a modular fashion are bus- 42 mastering data sources and bus-slave sinks, as depicted in Figure 2— 5. 2-micron CMOS process. , collecting error statistics and signal strength measurements). Conceptually, the architecture is analogous to an output-buffered, self-routing packet switch.

Selected protocol services and their performance and functional constraints On the other hand, the “performance” aspects of the protocol have softer correctness metrics that capture the probabilistic, common case behavior. We would like to characterize the average delay and queue length of the transmit path, for example. We would also like to know how well we are utilizing the available bandwidth, and how much we are wasting due to protocol overhead. These performance issues are best characterized using discrete event simulation.

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A methodology for the design and implementation of communication protocols for embedded wireless systems by Truman T.E.


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